Re: gEDA-user: Icarus Verilog with Xilinx simprims...

[John Griessen <john@xxxxxxxxxxxxxx>]

Andy Peters wrote:
the
> static timing analyzer (using your timing constraints) tells you if 
> you've met timing.  If both are good, there's no need to run a post-fit 
> simulation.
Dr. Deming told us that the Asian focus on direction of most closely approaching perfection
is a better goal than arbitrarily chosen accept/reject criteria American style.  Perhaps he was
thinking orientally?  Anyway, that wasn't his question.  He asked how to get the timing info into iverilog.

John Griessen

PS No specific knowledge of Xilinx, can't help, CSB.  (If I'm correct, those are
defined in the *.v files of the XILINX/verilog/src/simprims/
directory, one file for each module.)


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