Hi all,
I am trying to use Iverilog along with xilinx's SIMPRIMS. Well,
I managed, but I am getting strange results with simulations.
I'll try to explain how I'm doing this (I'm new to CPLDs, Verilog
and Icarus...)
First, I generate the post-fit verilog module from Xilinx ISE
project navigator. This is the .v file containing all the nets
and gates, for example X_AND2, etc... If I'm correct, those are
defined in the *.v files of the XILINX/verilog/src/simprims/
directory, one file for each module. They all contain timing
information, which is what I'm after. So, I add
"-y%XILINX%/verilog/src/simprims/" to my iverilog command,
and it generates no error. Then, I run vvp, and generate a VCD
from my testbench. So far, so good.
I open the VCD, but it seems like the timing information hasn't
been simulated. For example, there is no delay between a clock
event and a counter update, etc. The levels are all OK, states
are the same as the pre-synthesis simulation, so I really have
no clue of what's wrong.
One thing I've noticed is that the SIMPRIMS modules all have
a `timescale directive, the glbl.v file has a different one, and
my testbench is again different... could it be that some timing
gets "rounded" off ?
Thanks for any info,
Christian