gEDA-user: Iverilog synthesis problems

[Darren Stevens <darren@xxxxxxxxxxxxxxxxxxxxx>]

Hello All,

I've been trying to use a Digilent XLA development board fitted with a Xilinx
spartan XCS10 fitted.

Since the Xilinx free tools for this chip don't include a synthesis tool I've
been trying to use Iverilog, with some success.

This program can be compiled and converted to a bit file and works as
expected.

------

//Digilent xla test prog
module main( input sw1, sw2, output led1, led2);

wire sw1;
wire sw2;

reg led1;
reg led2;

$attribute(sw1, "PAD", "P28");
$attribute(sw2, "PAD", "P27");
$attribute(led1, "PAD", "P69");
$attribute(led2, "PAD", "P68");

always @(sw1 or sw2)
begin
    led1 = sw1;
    led2 = ~sw2;
end

endmodule

------

However when trying to make it a little more complicated i.e. adding gate
usage by changing the always block to:

always @(sw1 or sw2)
begin
    led1 = sw1 | sw2;
    led2 = sw1 & sw2;
end

causes ngdbuild to fail with the following errors:

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:486 - Attribute "INIT" is not allowed on symbol "U10" of type
   "LUT2".  This attribute will be ignored.
ERROR:NgdBuild:604 - logical block 'U10' with type 'LUT2' is unexpanded.
Symbol
   'LUT2' is not supported in target 'spartan'.
WARNING:NgdBuild:486 - Attribute "INIT" is not allowed on symbol "U9" of type
   "LUT2".  This attribute will be ignored.
ERROR:NgdBuild:604 - logical block 'U9' with type 'LUT2' is unexpanded. Symbol
   'LUT2' is not supported in target 'spartan'.

I'm at a bit of a loss where to go now, do I need to include some additional
library or is it something more obvious I'm missing?

I'm using the following command line to create an edf file, then importing
that as a source into the project navigator.

iverilog -tfpga -parch=virtex -oled.edf led.v

Kind regards
Darren


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