Re: gEDA-user: Iverilog synthesis problems

[Stephen Williams <steve@xxxxxxxxxx>]

Darren Stevens wrote:
> Hello All,
> 
> I've been trying to use a Digilent XLA development board fitted with a Xilinx
> spartan XCS10 fitted.
> 
> Since the Xilinx free tools for this chip don't include a synthesis tool I've
> been trying to use Iverilog, with some success.

I'm surprised by that. I thought the webpack releases support
spartan chips of various sort via xst. However, iverilog 0.8
should work too.


> 
> However when trying to make it a little more complicated i.e. adding gate
> usage by changing the always block to:
> 
> always @(sw1 or sw2)
> begin
>     led1 = sw1 | sw2;
>     led2 = sw1 & sw2;
> end
> 
> causes ngdbuild to fail with the following errors:
> 
> Checking timing specifications ...
> Checking expanded design ...
> WARNING:NgdBuild:486 - Attribute "INIT" is not allowed on symbol "U10" of type
>    "LUT2".  This attribute will be ignored.
> ERROR:NgdBuild:604 - logical block 'U10' with type 'LUT2' is unexpanded.
> Symbol
>    'LUT2' is not supported in target 'spartan'.
> WARNING:NgdBuild:486 - Attribute "INIT" is not allowed on symbol "U9" of type
>    "LUT2".  This attribute will be ignored.
> ERROR:NgdBuild:604 - logical block 'U9' with type 'LUT2' is unexpanded. Symbol
>    'LUT2' is not supported in target 'spartan'.

The -tfpga code generator for virtex is almost certainly trying
to implement your gates with LUT2 devices. It uses an INIT= attribute
attached to the LUT2 to specify the logic. That's pretty basic and
should work.

Looks like ngdbuild is not OK with LUT2 devices on spartan chips?
That is weird. What exactly is the software that comes with that
devel board? Can you use a recent Webpack instead?

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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