Re: gEDA-user: Iverilog synthesis problems

[Darren Stevens <darren@xxxxxxxxxxxxxxxxxxxxx>]

Hello Stephen

On 25/03/08, Stephen Williams wrote:
> The -tfpga code generator for virtex is almost certainly trying
> to implement your gates with LUT2 devices. It uses an INIT= attribute
> attached to the LUT2 to specify the logic. That's pretty basic and
> should work.
> 
> Looks like ngdbuild is not OK with LUT2 devices on spartan chips?
> That is weird. What exactly is the software that comes with that
> devel board? Can you use a recent Webpack instead?

Futher investigation reveals that this is the problem, I found what I think is
the component library used for the Spartan, and there is a text file with it
that seems to be a list of primitives. There are no entries for LUT of any
type, the closest I could find were fmap/hmap (mapping onto parts of the
CLB?) and ROM16x1.

There are however a very large number of logic gate entries, AND2, AND2B1,
AND2B2.. AND3 (up to 9 inputs IIRC) along with OR, NAND XOR etc..

So I editied the EDF file and changed the LUT2 entry to AND2 - ngdbuild was
quite happy with that. I even managed to add in OR2 and get the result I was
trying to from my original program.

The library I found seems to be the same for XC4000, spartan and spartan XL -
I suspect Xilinx changed it for the spartan II - hence why most of their
later tools won't work with it. The question is could I get a copy of the
spartanII.lib file and use that and still P&R the result?

Thanks
Darren


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user