Re: gEDA-user: Iverilog synthesis problems

[Stephen Williams <steve@xxxxxxxxxx>]

Darren Stevens wrote:
> Hello Stephen

> There are however a very large number of logic gate entries, AND2, AND2B1,
> AND2B2.. AND3 (up to 9 inputs IIRC) along with OR, NAND XOR etc..
> 
> So I editied the EDF file and changed the LUT2 entry to AND2 - ngdbuild was
> quite happy with that. I even managed to add in OR2 and get the result I was
> trying to from my original program.

The best thing to do in this case is to create am arch=spartan1
that uses ROM16x1 in place of LUTn and AND2 et al where reasonable.
This is done in the tgt-fpga directory of the source.

I don't know where your C programming skills are, but if you are
interested in working on this, take it over to the iverilog-devel
list and we can get you started. Or you can try to motivate one
of the regulars to do it for you.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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