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DJ Delorie wrote: I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoidhttp://www.xilinx.com/products/boards/ml410/index.htmlThey have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like "every connector goes directly to an FPGA pin". Maybe one fpga for the cpu core and one for the peripherals, though. more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may work without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. -Jesse |
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