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Re: gEDA-user: How to fit REFDES on PCB with Hierarchy
On Mon, 09 Mar 2009 07:39:29 -0400, gene wrote:
> With a hierarchical design, the refdes's are long and consuming a lot of
> board area. In some of the places, there just isn't enough room place
> them in a meaningful way. I know this has been kicked around before.
> Can anyone give me some suggestions on how to handle it?
For my medium complex projects I minimize the problem by giving the sub
sheets simple numbers. In addition, I set the separators to an empty
string in ~/.gEDA/gnetlistrc. This produces refdes strings like "5R24",
which translates to "resistor number 24 on page 5".
My gnetlistrc looks like this:
/------------------
(hierarchy-traversal "enabled")
(hierarchy-uref-mangle "enabled")
(hierarchy-uref-separator "")
(hierarchy-netname-mangle "enabled")
(hierarchy-netname-separator "")
(hierarchy-netattrib-mangle "disabled")
(hierarchy-netattrib-separator "/")
(unnamed-netname "noname")
(debug-options (list 'stack 200000))
(eval-options (list 'stack 200000))
\----------------------
---<(kaimartin)>---
--
Kai-Martin Knaak tel: +49-511-762-2895
Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211
Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de
GPG key: http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get
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