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Re: gEDA-user: [Icarus Verilog] How to synthesis a flip-flop with asynchronous reset

On Wed, Mar 11, 2009 at 11:12 AM, 温宇杰 <yujie.wen@xxxxxxxxxxxxxxxx> wrote:
>
> always @(posedge CLK or RESET) begin
> if (RESET == 1) begin Q = 0;
> end

I don't know much about iverilog but you may want to try this form:
always @(posedge CLK or posedge RESET) begin

Regards,
-r


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