Re: gEDA-user: FWD: Applying for GSoC2009

[msokolov@xxxxxxxxxxxxxxx (Michael Sokolov)]

sha liu <sandyleo26@xxxxxxxxx> wrote:

> Test are mostly run on our self-designed low-volume FPGA, but also on other
> popular commercial products.

Are you saying that you (your university group I guess) have fabbed your
own FPGA silicon?  Is it open source?  Is it comparable in capabilities
to the major commercial FPGAs like Brand A or Brand X?

As you may know the biggest bone in the throat of Open Source Hardware
is the secret nature of the configuration bitstream format for Brand A
and Brand X FPGAs.  Right now the only way to put your logic design into
a programmable logic device that's more capable than a 22V10 is to use
closed source software from A or X.  One can use open source tools like
Icarus Verilog to compile your RTL source into an EDIF netlist, but one
still has to then use the FPGA vendor's proprietary closed source
software for place&route and the actual bit file generation.  We can't
make an FOSS replacement for those proprietary tools because the
configuration bit format and even more fundamentally the precise
internal structure of the FPGA's logic and routing resources are secret.

Is ANYONE out there working on making a new FPGA that would be at least
somewhat comparable to A & X in capabilities, but have a fully publicly
documented internal structure and configuration bit format?

MS


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