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Re: gEDA-user: mcu to sdram interface project
DJ Delorie wrote:
> I finally got a verilog module that does a basic SDRAM interface (I
> talked about this a little at the last freedog meeting) so I started
> uploading stuff:
>
> http://www.delorie.com/electronics/sdram/
>
> Nothing fancy yet; it does an activate/transfer/precharge for every
> access the MCU makes. Perhaps later I'll add some smarts to it to get
> rid of the *one* read wait state it requires - the MCU has a 35ns
> setup time, so there's not much time to get the data out (and yes,
> that's an obvious spot to add a burst cache). The MCU only runs at
> 24MHz, the SDRAM is 133MHz (potentially asynchronous).
>
> Board's not done yet, but the interesting signals are routed
> (mcu-fpga-sdram).
Nice design - should be handy for giant RAM on small MCUs. I've
considered trying to hook SDRAM up through an FPGA as well, but the
complexity looked like it would eat up too many of the resources that I
wanted for other things.
It's interesting to compare the S3A with older parts. Nice that it can
get by without the 2.5V VCCAUX - generating & routing that on the
2-layer S3E design I did recently was a bit of a nuisance. I ended up
running the three supplies in a kind of 'snail-shell' concentric
topology in the back-side of the board directly under the FPGA package
which worked out nicely.
I'm a bit curious what happens if you forget to set the 3.3V
configuration bit - does it damage the part?
Xilinx docs have all sorts of dire warnings about proper decoupling of
the various supplies. I ended up putting a fair number of caps on the
back side of the board just to get them close enough to the package
pins. I haven't seen any issues with this in operation though, so it may
just be CYA.
For FPGA configuration I used slave serial mode and drove the DIN/CCLK
direct from a SPI port on my MCU - saved having to use Xilinx's special
configuration flash parts. Does mean that the start-up process is a bit
more complex though.
Eric
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