Re: gEDA-user: Skip DRC on "outline" layer

[Kai-Martin Knaak <kmk@xxxxxxxxxxxx>]

Kovacs Levente wrote:

> However, it is not a good idea to place vias close to the edge of
> the board.

Let's say, it depends. If the annular ring of the via is large, it 
may be perfectly fine to have it overlap with the outline. I did
this more than once for M3 holes. Sometimes it may even be desired
to have a plated hole on the center of the outline. The result is
a metalized cylindrical groove at the edge of the board. This can 
be used to solder the pcb to vertical edges of sheet metal.

The outline itself is not electrically conductive. Copper getting 
close to it cannot initiate short-circuits. So it should not be 
treated like it does. Distance of copper to outline should be a 
separate design rule with a distinct set of warnings. 

---<)kaimartin(>---
-- 
Kai-Martin Knaak
Email: kmk@xxxxxxxxxxxxxxx
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