Re: gEDA-user: Skip DRC on "outline" layer

[Colin D Bennett <colin@xxxxxxxxxxx>]

On Fri, 11 Mar 2011 02:32:06 +0100
Kai-Martin Knaak <kmk@xxxxxxxxxxxx> wrote:

> Kovacs Levente wrote:
> 
> > However, it is not a good idea to place vias close to the edge of
> > the board.

> Sometimes it may even be desired
> to have a plated hole on the center of the outline. The result is
> a metalized cylindrical groove at the edge of the board. This can 
> be used to solder the pcb to vertical edges of sheet metal.

That's interesting.  Do you have any examples of attaching a PCB to
sheet metal in this way?  Will the result also support making a module
or daughterboard such as, for example, the Microchip MRF24J40MA
<http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en535967>
which has scalloped âsolder cupsâ along two edges.

> The outline itself is not electrically conductive. Copper getting 
> close to it cannot initiate short-circuits. So it should not be 
> treated like it does. Distance of copper to outline should be a 
> separate design rule with a distinct set of warnings. 

A minimum-copper-to-outline DRC rule would be nice.  For instance
the DorkbotPDX PCB order has the constraint â15 mil clearances from
traces to the edge of the boardâ.  Currently I just manually ensure I
have enough space from traces to the edge.

Regards,
Colin


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