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Re: gEDA-user: Skip DRC on "outline" layer

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Subject: Re: gEDA-user: Skip DRC on "outline" layer
From: Mark Rages <markrages@xxxxxxxxx>
Date: Fri, 11 Mar 2011 09:41:10 -0600
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On Thu, Mar 10, 2011 at 7:34 AM, Thomas Oldbury <toldbury@xxxxxxxxx> wrote:
>   I am using an outline layer in PCB. It complains of DRC violations when
>   the outline is too close to vias. Is it possible to get it to skip DRC
>   on these?
>
>

Previous discussion: http://archives.seul.org/geda/user/Feb-2010/msg00209.html


-- 
Mark Rages, Engineer
Midwest Telecine LLC
markrages@xxxxxxxxxxxxxxxxxxx


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References:
- gEDA-user: Skip DRC on "outline" layer
  - From: Thomas Oldbury

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