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gEDA-user: Skip DRC on "outline" layer

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Subject: gEDA-user: Skip DRC on "outline" layer
From: Thomas Oldbury <toldbury@xxxxxxxxx>
Date: Thu, 10 Mar 2011 13:34:17 +0000
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   I am using an outline layer in PCB. It complains of DRC violations when
   the outline is too close to vias. Is it possible to get it to skip DRC
   on these?


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