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Re: gEDA-user: tb_ethernet.v



cfk wrote:

I am working today with the opencores ethernet project and trying to compile
with iverilog. I have gotten to the point where I can see an error I dont
understand. Basically, iverilog is telling me that on about line 2080 of
tb_ethernet.v where the statement says:

#Tp phy_data = {8'h7D, (i[7:0] + 1)};

Let me take a crack at this..

What is the bit size of (i[7:0] + 1) ? The IEEE spec doesn't define this - so that is an error in Icarus Verilog.
(Note to Steve Willliams...how did I do?) ;-)

Steve Wilson


the compiler says:

tb_ethernet.v:2080 error: operand of concatenation has indefinite width

Previously in the file at the beginning of 'task test_mii' near line 1400,
are the two declarations:

integer i;
reg [15:0] phy_data;

I believe this is a functioning test bench previously written for modelsim.
It appears to me that the concatenation is 8 bits for the constant 8'h7D and
8 bits for the lower 8 bits of the 32 bit integer i (i[7:0]). So, the
question is, why is iverilog complaining about this opencore project??