Re: gEDA-user: tb_ethernet.v

["cfk" <cfk@pacbell.net>]

Gentlemen:
    Thank you for your prompt and accurate response. Yes, the change from
(i[7:0] + 1) to (i[7:0] = 8'd1) causes iverilog to be much happier and I am
currently changing it in the 8 or so increments of phy_data throught the
test bench. I understand that the 8 bits of i can grow to 9 bits with a
carryout when i is maxed out. So, 8 + 9 > 16 and thats a problem. What
really puzzles me is why this is here in the first place. This particular
set of verilog modules is a released project at http://www.opencores.org and
the tb_ethernet.v file is reputed to be a completely functioning modelsim
testbench. I wonder of maybe modelsim accepts this syntax and quietly dumps
the carry bit and just goes on. That is worth a little more looking into
next week when I try to motivate one of my compatriots who actually has one
of our two modelsim dongles to try it.

    Again, thank you.