Re: gEDA-user: tb_ethernet.v

To: geda-user@seul.org
Subject: Re: gEDA-user: tb_ethernet.v
From: Gus Baldauf <gus@picturel.com>
Date: Fri, 23 May 2003 14:47:18 -0700
Delivered-to: archiver@seul.org
Delivered-to: geda-user-outgoing@seul.org
Delivered-to: geda-user@seul.org
Delivery-date: Fri, 23 May 2003 17:47:26 -0400
In-reply-to: <00d201c32173$0609ff60$6601a8c0@yang>
References: <200305231731.h4NHVdv22951@icarus.com> <00b301c3216e$d5311a30$6601a8c0@yang> <3ECE928B.8040104@spiketech.com> <00d201c32173$0609ff60$6601a8c0@yang>
Reply-to: geda-user@seul.org
Sender: owner-geda-user@seul.org
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.3) Gecko/20030312

cfk wrote:

I understand that the 8 bits of i can grow to 9 bits with a
carryout when i is maxed out. So, 8 + 9 > 16 and thats a problem.

I don't think you will get the 9th bit. I don't think verilog will automagically resize your vector from 8 to 9 bits.

Not a verilog expert, Gus

References:
- Re: gEDA-user: Icarus Verilog, convert_hex2ver and VPI
  - From: Stephen Williams <steve@icarus.com>
- gEDA-user: tb_ethernet.v
  - From: "cfk" <cfk@pacbell.net>
- Re: gEDA-user: tb_ethernet.v
  - From: Steve Wilson <steve@spiketech.com>
- Re: gEDA-user: tb_ethernet.v
  - From: "cfk" <cfk@pacbell.net>