Re: gEDA-user: tb_ethernet.v

[Stephen Williams <steve@icarus.com>]

cfk@pacbell.net said:
> phy_data = {8'h7D, (i[7:0] + 1)};

cfk@pacbell.net said:
> I wonder of maybe modelsim accepts this syntax and quietly dumps the
> carry bit and just goes on.

Much worse then that, in some cases. I think ncverilog will
turn the above expression into the 40bit expression:

    {8'h7d, ( {24'h00_00_00, i[7:0]}, + 32'd1 )}

Then the low 16 bits of that are assigned to phy_data. Modelsim
may well handle this differently, and that just compounds the
headaches.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
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