Re: gEDA-user: Assertion based verification using VCD and VHDL

[Peter Kaiser <peter@easy-asic.de>]

Hi, 

I also work on a open source tool chain for mixed signal asics. Unfortunatly I 
don't know a tool that converts VCD to VHDL or Verilog.  My ASIC's are 80% 
analog with only a small digital part to control e.g. SC amplifier.
May I ask you 2 questions: 
- What Spice do you use?
- How do you come from Spice output (raw) to vcd?


>
> Finally, is there a better way to verify the operation of a
> digital circuit simulation done using SPICE?
>

At the moment I still use proprietary digital simulators for this, but my plan 
is to test icarus verilog in the future.

Would be nice, if you stay with open source tools and gEDA. I am interested in 
excanging experiance about this tool chain.


Peter