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gEDA-user: Verilog netlister for Icarus Verilog?

To: geda-user@xxxxxxxx
Subject: gEDA-user: Verilog netlister for Icarus Verilog?
From: "Harold D. Skank" <skank54@xxxxxxxxx>
Date: Mon, 02 May 2005 11:20:23 -0500
Cc: "Skank, Harold" <skank54@xxxxxxxxx>
Delivered-to: archiver@seul.org
Delivered-to: geda-user-outgoing@seul.org
Delivered-to: geda-user@seul.org
Delivery-date: Mon, 02 May 2005 12:18:34 -0400
Reply-to: geda-user@xxxxxxxx
Sender: owner-geda-user@xxxxxxxx

People,

I have been working for several days now, trying to get Icarus Verilog
up and running.  Since I am using the gEDA open-source tools, I set
things up to use gschem for schematic capture, assuming that I could use
gnetlist to generate the netlist for Icarus Verilog.  Well, it looked
like things were working, until I started to try to run simulations, at
which point I started getting strange warnings and errors in Verilog.  I
think I finally traced the problem to the fact that the netlisting
program from gEDA generates "connection by ordered list", while Icarus Verilog
apparently wants "connection by name."

I have attached an example of a module that I created using gschem and
gnetlist as indicated in the gEDA Verilog netlister README.  Along with that
I have also attached an output from the Icarus Verilog compiler showing
the warnings and errors that were produced.  A third attached file is a
modified version of that produced by the gEDA netlister in which I have
manually changed the references to "connection by name."  While I
apparently have problems in my logic, Icarus Verilog compiles this program and its
simulation runs and produces output.

Now, if I recall correctly, Verilog is supposed to accept either version
of the connections, but according to the material from Steven Williams,
he has difficulty sorting out the "connection by ordered list" so has
adopted "connection by name."  Now, is it possible that there exists
another scheme file that will generate the netlist that I need?

Any suggestions would be greatly appreciated.

	Regards,

	Harold Skank

/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id: gnet-verilog.scm,v 1.13 2004/12/20 19:30:48 mike Exp $ */
/* Source.......$Source: /home/cvspsrv/cvsroot/eda/geda/devel/gnetlist/scheme/gnet-verilog.scm,v $ */
/* Revision.....$Revision: 1.13 $ */
/* Author.......$Author: mike $ */

module CGU13 (
       LD ,
       EN ,
       CD ,
       CLK ,
       D0 ,
       D1 ,
       D2 ,
       Q0 ,
       Q1 ,
       Q2
      );

/* Port directions begin here */
input LD ;
input EN ;
input CD ;
input CLK ;
input D0 ;
input D1 ;
input D2 ;
output Q0 ;
output Q1 ;
output Q2 ;


/* Wires from the design */
wire HOLD2 ;
wire unnamed_net10 ;
wire HOLD1 ;
wire unnamed_net9 ;
wire LDN ;
wire HOLD0 ;
wire LOAD0 ;
wire unnamed_net8 ;
wire LOAD1 ;
wire LOAD2 ;
wire LD ;
wire CD ;
wire CLK ;
wire Q0 ;
wire D0 ;
wire unnamed_net7 ;
wire unnamed_net6 ;
wire unnamed_net5 ;
wire unnamed_net4 ;
wire D1 ;
wire Q1 ;
wire QI1N ;
wire D2 ;
wire Q2 ;
wire unnamed_net3 ;
wire QI0 ;
wire QI2N ;
wire EN ;
wire unnamed_net2 ;
wire QI0N ;
wire QI1 ;
wire unnamed_net1 ;
wire QI2 ;
wire ENN ;

/* continuous assignments */

/* Package instantiations */
FD21 U63 ( 
  /* D0 */ unnamed_net9,
  /* Q0 */ QI1,
  /* CLK */ CLK,
  /* CD */ CD
    );

FD21 U60 ( 
  /* D0 */ unnamed_net8,
  /* Q0 */ QI0,
  /* CLK */ CLK,
  /* CD */ CD
    );

FD21 U67 ( 
  /* D0 */ unnamed_net10,
  /* Q0 */ QI2,
  /* CLK */ CLK,
  /* CD */ CD
    );

AND2 U69 ( 
  /* A0 */ D0,
  /* A1 */ LD,
  /* Z0 */ LOAD0
    );

AND3 U68 ( 
  /* A1 */ LDN,
  /* A2 */ ENN,
  /* Z0 */ HOLD2,
  /* A0 */ QI2
    );

OR5 U66 ( 
  /* Z0 */ unnamed_net10,
  /* A1 */ LOAD2,
  /* A3 */ unnamed_net2,
  /* A2 */ unnamed_net1,
  /* A0 */ HOLD2,
  /* A4 */ unnamed_net3
    );

AND3 U65 ( 
  /* A1 */ LDN,
  /* A2 */ ENN,
  /* Z0 */ HOLD1,
  /* A0 */ QI1
    );

OR4 U64 ( 
  /* Z0 */ unnamed_net9,
  /* A1 */ LOAD1,
  /* A2 */ QI1,
  /* A0 */ HOLD1,
  /* A3 */ unnamed_net4
    );

INV U62 ( 
  /* A0 */ LD,
  /* ZN0 */ LDN
    );

AND3 U61 ( 
  /* A1 */ LDN,
  /* A2 */ ENN,
  /* Z0 */ HOLD0,
  /* A0 */ QI0
    );

OR5 U59 ( 
  /* Z0 */ unnamed_net8,
  /* A1 */ LOAD0,
  /* A3 */ unnamed_net6,
  /* A2 */ unnamed_net5,
  /* A0 */ HOLD0,
  /* A4 */ unnamed_net7
    );

AND2 U58 ( 
  /* A0 */ D1,
  /* A1 */ LD,
  /* Z0 */ LOAD1
    );

AND2 U57 ( 
  /* A0 */ D2,
  /* A1 */ LD,
  /* Z0 */ LOAD2
    );

INV U56 ( 
  /* A0 */ EN,
  /* ZN0 */ ENN
    );

BUF U55 ( 
  /* A0 */ QI0,
  /* Z0 */ Q0
    );

INV U54 ( 
  /* A0 */ QI0,
  /* ZN0 */ QI0N
    );

AND3 U53 ( 
  /* A1 */ QI2N,
  /* A2 */ QI0,
  /* Z0 */ unnamed_net7,
  /* A0 */ EN
    );

AND3 U52 ( 
  /* A1 */ QI2,
  /* A2 */ QI1N,
  /* Z0 */ unnamed_net6,
  /* A0 */ EN
    );

AND2 U51 ( 
  /* A0 */ ENN,
  /* A1 */ QI0,
  /* Z0 */ unnamed_net5
    );

AND3 U50 ( 
  /* A1 */ QI2,
  /* A2 */ QI0,
  /* Z0 */ unnamed_net4,
  /* A0 */ EN
    );

BUF U49 ( 
  /* A0 */ QI1,
  /* Z0 */ Q1
    );

INV U48 ( 
  /* A0 */ QI1,
  /* ZN0 */ QI1N
    );

BUF U47 ( 
  /* A0 */ QI2,
  /* Z0 */ Q2
    );

INV U46 ( 
  /* A0 */ QI2,
  /* ZN0 */ QI2N
    );

AND3 U45 ( 
  /* A1 */ QI2N,
  /* A2 */ QI0,
  /* Z0 */ unnamed_net3,
  /* A0 */ EN
    );

AND3 U44 ( 
  /* A1 */ QI1,
  /* A2 */ QI0N,
  /* Z0 */ unnamed_net2,
  /* A0 */ EN
    );

AND2 U43 ( 
  /* A0 */ ENN,
  /* A1 */ QI2,
  /* Z0 */ unnamed_net1
    );

endmodule

[designer@AMD cgu13]$ ./vlogLSI
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:10: warning: timescale for CGU13 inherited from another file.
testfixture.v:6: ...: The inherited timescale is here.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/fd21.v:14: warning: implicit definition of wire testfixture.dut.U63.t1.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/fd21.v:15: warning: implicit definition of wire testfixture.dut.U63.t2.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/fd21.v:14: warning: implicit definition of wire testfixture.dut.U60.t1.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/fd21.v:15: warning: implicit definition of wire testfixture.dut.U60.t2.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/fd21.v:14: warning: implicit definition of wire testfixture.dut.U67.t1.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/fd21.v:15: warning: implicit definition of wire testfixture.dut.U67.t2.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:97: warning: L-value ``D0'' is also an input port.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:51: warning: input D0; is coerced to inout.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:134: warning: L-value ``LD'' is also an input port.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:47: warning: input LD; is coerced to inout.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:155: warning: L-value ``D1'' is also an input port.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:56: warning: input D1; is coerced to inout.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:161: warning: L-value ``D2'' is also an input port.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:59: warning: input D2; is coerced to inout.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:167: warning: L-value ``EN'' is also an input port.
/tools/Lattice/isptools/kits/isplsi/verilog/library/lsc/cgu13.v:64: warning: input EN; is coerced to inout.
testfixture.v:17: error: reg LD; cannot be driven by primitives or continuous assignment.
testfixture.v:17: error: Output port expression must support continuous assignment.
testfixture.v:17:      : Port of CGU13 is LD
testfixture.v:17: error: reg EN; cannot be driven by primitives or continuous assignment.
testfixture.v:17: error: Output port expression must support continuous assignment.
testfixture.v:17:      : Port of CGU13 is EN
testfixture.v:17: error: reg D0; cannot be driven by primitives or continuous assignment.
testfixture.v:17: error: Output port expression must support continuous assignment.
testfixture.v:17:      : Port of CGU13 is D0
testfixture.v:17: error: reg D1; cannot be driven by primitives or continuous assignment.
testfixture.v:17: error: Output port expression must support continuous assignment.
testfixture.v:17:      : Port of CGU13 is D1
testfixture.v:17: error: reg D2; cannot be driven by primitives or continuous assignment.
testfixture.v:17: error: Output port expression must support continuous assignment.
testfixture.v:17:      : Port of CGU13 is D2
10 error(s) during elaboration.
[designer@AMD cgu13]$

/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id: gnet-verilog.scm,v 1.13 2004/12/20 19:30:48 mike Exp $ */
/* Source.......$Source: /home/cvspsrv/cvsroot/eda/geda/devel/gnetlist/scheme/gnet-verilog.scm,v $ */
/* Revision.....$Revision: 1.13 $ */
/* Author.......$Author: mike $ */

module CGU13 (
       LD ,
       EN ,
       CD ,
       CLK ,
       D0 ,
       D1 ,
       D2 ,
       Q0 ,
       Q1 ,
       Q2
      );

/* Port directions begin here */
input LD ;
input EN ;
input CD ;
input CLK ;
input D0 ;
input D1 ;
input D2 ;
output Q0 ;
output Q1 ;
output Q2 ;


/* Wires from the design */
wire HOLD2 ;
wire unnamed_net10 ;
wire HOLD1 ;
wire unnamed_net9 ;
wire LDN ;
wire HOLD0 ;
wire LOAD0 ;
wire unnamed_net8 ;
wire LOAD1 ;
wire LOAD2 ;
wire LD ;
wire CD ;
wire CLK ;
wire Q0 ;
wire D0 ;
wire unnamed_net7 ;
wire unnamed_net6 ;
wire unnamed_net5 ;
wire unnamed_net4 ;
wire D1 ;
wire Q1 ;
wire QI1N ;
wire D2 ;
wire Q2 ;
wire unnamed_net3 ;
wire QI0 ;
wire QI2N ;
wire EN ;
wire unnamed_net2 ;
wire QI0N ;
wire QI1 ;
wire unnamed_net1 ;
wire QI2 ;
wire ENN ;

/* continuous assignments */

/* Package instantiations */
AND2 U69 (.Z0(LOAD0),.A0(D0),.A1(LD));
//  /* A0 */ D0,
//  /* A1 */ LD,
//  /* Z0 */ LOAD0
//    );

AND3 U68 (.Z0(HOLD2),.A0(QI2),.A1(LDN),.A2(ENN));
//  /* A1 */ LDN,
//  /* A2 */ ENN,
//  /* Z0 */ HOLD2,
//  /* A0 */ QI2
//    );

FD21 U67 (.Q0(QI2),.D0(unnamed_net10),.CLK(CLK),.CD(CD));
//  /* D */ unnamed_net10,
//  /* Q */ QI2,
//  /* CLK */ CLK,
//  /* CD */ CD
//    );

OR5 U66 (.Z0(unnamed_net10),.A0(HOLD2),.A1(LOAD2),.A2(unnamed_net1),.A3(unnamed_net2),.A4(unnamed_net3));
//  /* Z0 */ unnamed_net10,
//  /* A1 */ LOAD2,
//  /* A3 */ unnamed_net2,
//  /* A2 */ unnamed_net1,
//  /* A0 */ HOLD2,
//  /* A4 */ unnamed_net3
//    );

AND3 U65 (.Z0(HOLD1),.A0(QI1),.A1(LDN),.A2(ENN));
//  /* A1 */ LDN,
//  /* A2 */ ENN,
//  /* Z0 */ HOLD1,
//  /* A0 */ QI1
//    );

OR4 U64 (.Z0(unnamed_net9),.A0(HOLD1),.A1(LOAD1),.A2(QI1),.A3(unnamed_net4));
//  /* Z0 */ unnamed_net9,
//  /* A1 */ LOAD1,
//  /* A2 */ QI1,
//  /* A0 */ HOLD1,
//  /* A3 */ unnamed_net4
//    );

FD21 U63 (.Q0(QI1),.D0(unnamed_net9),.CLK(CLK),.CD(CD));
//  /* D */ unnamed_net9,
//  /* Q */ QI1,
//  /* CLK */ CLK,
//  /* CD */ CD
//    );

INV U62 (.ZN0(LDN),.A0(LD));
//  /* A0 */ LD,
//  /* ZN0 */ LDN
//    );

AND3 U61 (.Z0(HOLD0),.A0(QI0),.A1(LDN),.A2(ENN));
//  /* A1 */ LDN,
//  /* A2 */ ENN,
//  /* Z0 */ HOLD0,
//  /* A0 */ QI0
//    );

FD21 U60 (.Q0(QI0),.D0(unnamed_net8),.CLK(CLK),.CD(CD));
//  /* D */ unnamed_net8,
//  /* Q */ QI0,
//  /* CLK */ CLK,
//  /* CD */ CD
//    );

OR5 U59 (.Z0(unnamed_net8),.A0(HOLD0),.A1(LOAD0),.A2(unnamed_net5),.A3(unnamed_net6),.A4(unnamed_net7));
//  /* Z0 */ unnamed_net8,
//  /* A1 */ LOAD0,
//  /* A3 */ unnamed_net6,
//  /* A2 */ unnamed_net5,
//  /* A0 */ HOLD0,
//  /* A4 */ unnamed_net7
//    );

AND2 U58 (.Z0(LOAD1),.A0(D1),.A1(LD));
//  /* A0 */ D1,
//  /* A1 */ LD,
//  /* Z0 */ LOAD1
//    );

AND2 U57 (.Z0(LOAD2),.A0(D2),.A1(LD));
//  /* A0 */ D2,
//  /* A1 */ LD,
//  /* Z0 */ LOAD2
//    );

INV U56 (.ZN0(ENN),.A0(EN));
//  /* A0 */ EN,
//  /* ZN0 */ ENN
//    );

BUF U55 (.Z0(Q0),.A0(QI0));
//  /* A0 */ QI0,
//  /* Z0 */ Q0
//    );

INV U54 (.ZN0(QI0N),.A0(QI0));
//  /* A0 */ QI0,
//  /* ZN0 */ QI0N
//    );

AND3 U53 (.Z0(unnamed_net7),.A0(EN),.A1(QI2N),.A2(QI0));
//  /* A1 */ QI2N,
//  /* A2 */ QI0,
//  /* Z0 */ unnamed_net7,
//  /* A0 */ EN
//    );

AND3 U52 (.Z0(unnamed_net6),.A0(EN),.A1(QI2),.A2(QI1N));
//  /* A1 */ QI2,
//  /* A2 */ QI1N,
//  /* Z0 */ unnamed_net6,
//  /* A0 */ EN
//    );

AND2 U51 (.Z0(unnamed_net5),.A0(ENN),.A1(QI0));
//  /* A0 */ ENN,
//  /* A1 */ QI0,
//  /* Z0 */ unnamed_net5
//    );

AND3 U50 (.Z0(unnamed_net4),.A0(EN),.A1(QI2),.A2(QI0));
//  /* A1 */ QI2,
//  /* A2 */ QI0,
//  /* Z0 */ unnamed_net4,
//  /* A0 */ EN
//    );

BUF U49 (.Z0(Q1),.A0(QI1));
//  /* A0 */ QI1,
//  /* Z0 */ Q1
//    );

INV U48 (.ZN0(QI1N),.A0(QI1));
//  /* A0 */ QI1,
//  /* ZN0 */ QI1N
//    );

BUF U47 (.Z0(Q2),.A0(QI2));
//  /* A0 */ QI2,
//  /* Z0 */ Q2
//    );

INV U46 (.ZN0(QI2N),.A0(QI2));
//  /* A0 */ QI2,
//  /* ZN0 */ QI2N
//    );

AND3 U45 (.Z0(unnamed_net3),.A0(EN),.A1(QI2N),.A2(QI0));
//  /* A1 */ QI2N,
//  /* A2 */ QI0,
//  /* Z0 */ unnamed_net3,
//  /* A0 */ EN
//    );

AND3 U44 (.Z0(unnamed_net2),.A0(EN),.A1(QI1),.A2(QI0N));
//  /* A1 */ QI1,
//  /* A2 */ QI0N,
//  /* Z0 */ unnamed_net2,
//  /* A0 */ EN
//    );

AND2 U43 (.Z0(unnamed_net1),.A0(ENN),.A1(QI2));
//  /* A0 */ ENN,
//  /* A1 */ QI2,
//  /* Z0 */ unnamed_net1
//    );

endmodule

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