Re: gEDA-user: Verilog netlister for Icarus Verilog?

[Mike Jarabek <mjarabek@xxxxxxxxx>]

Hi,

"Harold D. Skank" wrote:

People,

I have been working for several days now, trying to get Icarus Verilog
up and running.  Since I am using the gEDA open-source tools, I set
things up to use gschem for schematic capture, assuming that I could use
gnetlist to generate the netlist for Icarus Verilog.  Well, it looked
like things were working, until I started to try to run simulations, at
which point I started getting strange warnings and errors in Verilog.  I
think I finally traced the problem to the fact that the netlisting
program from gEDA generates "connection by ordered list", while Icarus Verilog
apparently wants "connection by name."

You can have it both ways.  If you add an unnatached attribute `VERILOG_PORTS=POSITIONAL'
onto the symbol the netlister will output what you have posted.  If
you do not have that attribute present or attached to your symbols then
the netlister will output the ports in the named port format. (eg. 
.name(signal) )  I added that attribute `switch' to allow the
netlister to output the verilog gate primitives.

 

I have attached an example of a module that I created using gschem and
gnetlist as indicated in the gEDA Verilog netlister README.  Along with that
I have also attached an output from the Icarus Verilog compiler showing
the warnings and errors that were produced.  A third attached file is a
modified version of that produced by the gEDA netlister in which I have
manually changed the references to "connection by name."  While I
apparently have problems in my logic, Icarus Verilog compiles this program and its
simulation runs and produces output.

With the above mentioned attribute removed, you should be able to netlist
with the ports named. If this does not work can you post an example schematic
and symbol file that does not work correctly? As this would be a bug.

 

Now, if I recall correctly, Verilog is supposed to accept either version
of the connections, but according to the material from Steven Williams,
he has difficulty sorting out the "connection by ordered list" so has
adopted "connection by name."  Now, is it possible that there exists
another scheme file that will generate the netlist that I need?

Any suggestions would be greatly appreciated.

        Regards,

        Harold Skank

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-- 
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                              Mike Jarabek        
                                FPGA/ASIC Designer
  http://www.istop.com/~mjarabek                    
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