Re: gEDA-user: Via inner layer clears

[David Carr <dc@xxxxxxxxx>]

I did a bit more reading and found this related post:
http://groups.google.com/group/sci.electronics.cad/browse_thread/thread/c383750ba60350b8/9ea4f6c30f9cc7c4?lnk=st&q=inner+layer+via+clearance&rnum=1&hl=en#9ea4f6c30f9cc7c4

It turns out that removing the inner layer pads doesn't buy you anything
due to the fact that the holes are drilled oversize before plating...
bummer.

-DC

David Carr wrote:

>    I've been playing around with vias on multi-layer boards in PCB. 
>I'm using vias with a 15mil hole and a 5mil annular ring for a total dia
>of 25mils.  My test board has 4 layers and I have placed several vias
>that connect to no layers.  On the outermost layers the vias clear an
>area about 37 mils in diameter.  This makes sense because I have 6mil
>spacing so 2*6mils + 25mils = 37 mils total clearance.  However, on the
>inner board layers (which are not connected to these vias) the clearance
>is also 37 mils.  It seems to me that since the drill is only 15mils and
>I have 6 mil spacing, I should be able to have the via only clear 2*6 +
>15 = 27 mils on the inner layers.
>
>Is there a flaw in my logic or my board layout?  I'd really like to have
>those extra 10mils back on unconnected inner layers.
>
>Thanks,
>David Carr
>  
>