Re: gEDA-user: Verilog, testbenches, and Makefiles

[Günter Dannoritzer <dannoritzer@xxxxxx>]

Dan McMahill wrote:
[...]
> 
> \begin{shamelessplug}
> 
> If you're doing LateX documents and like Makefile's you might take a 
> look at latex-mk (http://latex-mk.sf.net).  It is a set of makefile 
> fragments along with a couple of wrapper scripts.  It manages 
> dependencies and all the building needed for complex documents.

Hi Dan,

Thanks for the information. I haven't known about this one yet.

I will look into it. My first step for now is that I have created a RPM 
package for openSUSE, available through here:

http://software.opensuse.org/search

BTW, this is now going more towards logic development, but fits into the 
Makefile idea, I ran across this tool that extracts register information 
from a document and creates the Verilog code:

http://www.veripool.org/wiki/vregs

It also supports the extraction from LaTex and I was wondering whether 
someone has already some experience with it?

Cheers,

Guenter



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