Re: gEDA-user: fritzing

[Joerg <joergsch@xxxxxxxxxxxxxxxxxxxxx>]

Eric Brombaugh wrote:
> Joerg wrote:
>> Eric Brombaugh wrote:
>>> John Griessen wrote:
>>>> How about the code intensive hardware system developers that start
>>>> a project with FPGA then migrate it to ASIC?  What language do they use -- c++?
>>> Typically they'll use a HDL like Verilog or VHDL. Those are generally 
>>> compatible across FPGAs and ASICs alike. There have been attempts to use 
>>> C++ for hardware design, but they haven't found their way into the 
>>> mainstream.
>>>
>> C++ for hardware design?
>>
>> <getting goose bumps>
> 
> Yep - typically involves building a big class library to support things 
> like clocked processes and basic RTL structures & methods. The results 
> end up looking a lot like most other HDLs and don't really run much 
> faster. And of course this requires a translation shim to get it into 
> any normal ASIC or FPGA synthesis/PAR toolflow.
> 
> As Stuart notes, you can operate at a higher level than some of the 
> older spec'd HDLs, but a lot of higher functionality has been rolled 
> into Verilog2k in the meantime so it's tough to say how much of an 
> advantage it is.
> 
> And of course it has the disadvantage of allowing software types think 
> that they can design hardware without any additional training. :) (ducks)
> 

Shhht! That's the bread and butter of my business ...

-- 
Regards, Joerg

http://www.analogconsultants.com/



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