gEDA-user: Breadboard drawings with pcb?

[Josef Wolf <jw@xxxxxxxxxxxxx>]

Hello,

I am about to write an introduction into electronics for kids.  This
introduction will also contain small circuits to experiment with.  For
building the circuits, I'd use a breadboard like this one:

http://produkt.conrad.de/45973183/steckplatine-eic-108.htm

To draw the schematics, I'd use gschem (obviously).  But I wonder how
to create the drawings for placing the components.  I'd like to have
the holes and connections of the breadboard be drawn in light-grey.  On
top of that, I'd draw the actual components and the paths of the current
in black.

I can think of two ways of doing this:

1. Create the breadboard drawing as a component on its own, so it would be
   included into gschem.  This method would probably clutter the schematic
   with a useless component.

2. Add the breadboard as a drawing into pcb.  I've done a little perl
   script just to see how this could look like.  I've attached the script
   below.


Now here are my questions:

- How can I make the breadboard drawing appear light-grey in pcb's
  postscript output?
- Is there a way to make pcb aware of the fact that the holes in the
  breadboard are connected?
- Any other suggestions?



#! /usr/bin/perl

use strict;
use warnings;

my @texts;
my ($rows, $cols) = (shift, shift);
$rows = 2 unless defined $rows;
$cols = 1 unless defined $cols;

&header;

sub text {
    my ($x, $y, $text) = @_;
    push (@texts, sprintf ('Text[%d %d 0 100 "%s" ""]',
                           ($x*10000, $y*10000, $text)));
}

for (my $c=0; $c<($cols+1)*18; $c+=18) {
    if ($c<$cols*18) {
        my %off=(A=>5,  B=>6,  C=>7,  D=>8,  E=>9,
                 F=>12, G=>13, H=>14, I=>15, J=>16);
        foreach my $arr (0, $rows*6+3.4) {
            foreach my $l ("A".."J") {
                &text ($c+$off{$l}-0.12, $arr, $l);
            }
        }
    }
    for (my $r=0; $r<$rows*6+3; $r++) {
        unless (($r-3)%6) {
            &vbar ($c+1, $r);
            &vbar ($c+2, $r)
        }
        if ($c<$cols*18) {
            &hbar ($c+5,  $r+1);
            &hbar ($c+12, $r+1);
            foreach my $x (4, 16.5) {
                if ($r==1 || $r%5==0) {
                    &text ($c+$x, $r-0.3, $r);
                }
            }
        }
    }
}

&footer;

sub vbar {
    my ($x, $y, $o) = @_;
    $x *= 10000;
    $y *= 10000;
    
    print <<_EOF_;
    Element["" "vLine5" "" "vLINE5" $x $y 0 0 0 100 ""]
        (
         Pin[0     0 6000 3000 6600 3800 "1" "1" ""]
         Pin[0 10000 6000 3000 6600 3800 "2" "2" ""]
         Pin[0 20000 6000 3000 6600 3800 "3" "3" ""]
         Pin[0 30000 6000 3000 6600 3800 "4" "4" ""]
         Pin[0 40000 6000 3000 6600 3800 "5" "5" ""]
         ElementLine [0 40000 0 0 1000]
	)
_EOF_
}

sub hbar {
    my ($x, $y, $o) = @_;
    $x *= 10000;
    $y *= 10000;
    
    print <<_EOF_;
    Element["" "hLine5" "" "hLINE5" $x $y 0 0 0 100 ""]
        (
         Pin[    0 0 6000 3000 6600 3800 "1" "1" ""]
         Pin[10000 0 6000 3000 6600 3800 "2" "2" ""]
         Pin[20000 0 6000 3000 6600 3800 "3" "3" ""]
         Pin[30000 0 6000 3000 6600 3800 "4" "4" ""]
         Pin[40000 0 6000 3000 6600 3800 "5" "5" ""]
         ElementLine [0 0 40000 0 1000]
	)
_EOF_
}

sub header {
    my $x = $cols*180000+30000;
    my $y = $rows*60000+50000;
    print <<_EOF_;
    FileVersion[20070407]

        PCB["" $x $y]

        Grid[10000.000000 0 0 1]
        Cursor[0 0 0.000000]
        PolyArea[200000000.000000]
        Thermal[0.500000]
        DRC[1000 1000 1000 1000 1500 1000]
        Flags("nameonpcb,uniquename,clearnew,snappin")
        Groups("1,c:2,s:3:4:5:6:7:8")
        Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
_EOF_
}

sub footer {
    my $texts = join ("\n", "", @texts, "");
    print <<_EOF_;
        Layer(1 "component") ( $texts )
        Layer(2 "solder")    ( )
        Layer(3 "GND")       ( )
        Layer(4 "power")     ( )
        Layer(5 "signal1")   ( )
        Layer(6 "signal2")   ( )
        Layer(7 "signal3")   ( )
        Layer(8 "signal4")   ( )
        Layer(9 "silk")      ( )
        Layer(10 "silk")     ( )
_EOF_
}


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