Re: gEDA-user: pcb: Track routing strategies and tips

[Gabriel Paubert <paubert@xxxxxxx>]

On Wed, May 11, 2011 at 02:26:43AM +0200, Kai-Martin Knaak wrote:
> Colin D Bennett wrote:
> 
> > Does anyone have any tips on how to plan a layout for easy and clean
> > track routing?  In particular for 2-layer boards.
> 
> Put extra care into component placement. IMHO, placement is more 
> critical to the design than routing.

Indeed. I've been told y a professional (her job is to lay out
PCB with expensive commercial tools) that she has never seen a 
good or even acceptable automatic placer. However she claims
that automatic routers are now reasonably good, far from perfect,
but the help.

I have very similar problems in FPGAs: I often can only 
reach the performance I want when helping by fixing the
location of the large blocks (mostly RAM and DSP).

> 
> 
> > One strategy that I have seen and recently tried is to use the top
> > layer for all horizontal trace runs and the bottom layer for all
> > vertical trace runs, or vice-versa.
> 
> Yep. This is a good default. It avoids road blocks by tracks on
> both sides.

It's called Manhattan routing. It's a good starting point,
but you should at least perform some via reduction run at some
later stage.

> 
> 
> > Do you ever use the pcb autorouter 
> 
> Rarely.

Basically only for fun...

> 
> 
> > or do you always route by hand?
> 
> Mostly.

Always in practice, but that's because my circuits are simple
but almost invariably involve microstrip and/or coplanar line
for the most important signals (and mechanical design of the
enclosure is as critical as the PCB layout).

I'm in the process of designing a much more complex board
with FPGA, DDS and no real high frequency signal (highest 
frequency being the 400MHz DDS clock). But the layout is 
going to be done by the person mentioned above (using 
CadStar at the moment).

BTW, there is no gschem->CadStar netlister, or did I miss it?

	Gabriel


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