Re: gEDA-user: sintesis tool

["Shing-Fat (Fred) Ma" <fma@doe.carleton.ca>]

Hello,

I recall a tool by a company called Cadabra (Ottawa based, possibly bought out already).
It did migration of cells from one technology to another (basically, relayout according to
guidance rules ).  I haven't
kept up or delved into it, but if you can synthesize to any library, perhaps you can
retarget it to another (hypothetical) cell library.

Fred

Matteo Poletti wrote:

>  Hi,
>
> I'm searching a tool which can sintetise from a behavioral description (VHDL or Verilog) to a cmos level. The circuits are not larger than 1000 gate's and are for ASIC applications.
>
> gEDA is able to do this?
>
> I tried Alliance but I it accepts only strictly structural VHDL.
>
> Can you help me?
>
> Thank you in advance
>
> Matteo Poletti
>
>
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--
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Fred Ma
Department of Electronics
Carleton University, Mackenzie Building
1125 Colonel By Drive
Ottawa, Ontario
Canada     K1S 5B6
fma@doe.carleton.ca
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