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gEDA-user: sintesis tool
Hi,
I'm searching a tool which can sintetise from a behavioral description
(VHDL or Verilog) to a cmos level. The circuits are not larger than 1000
gate's and are for ASIC applications.
gEDA is able to do this?
I tried Alliance but I it accepts only strictly structural
VHDL.
Can you help me?
Thank you in advance
Matteo Poletti
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_/ _/ _/
_/ Matteo
Poletti _/
Tel1: +39 0382
301870 _/
_/ Acco Microelettronica S.r.l._/ Tel2: +39 0382
307455 _/
_/ Via Vittorio Emanuele II, 5 _/ Fax :
+39 0382
301870 _/
_/ 27100 Pavia
(PV) _/
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_/
Italy _/ _/
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mailto:
m.poletti@acco-ic.it _/
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