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Re: gEDA-user: one schmatic ==> two netlist
- To: geda-user@seul.org
- Subject: Re: gEDA-user: one schmatic ==> two netlist
- From: Bill Cox <bill@viasic.com>
- Date: Sat, 01 Nov 2003 04:39:40 -0500
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- Delivery-date: Sat, 01 Nov 2003 05:29:03 -0500
- In-reply-to: <200311010010.55271.die.kaisers@t-online.de>
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Familie Kaiser wrote:
Thank's for the quick answer.
I need the Spice netlist not only for simulation, I need it also for LVS
(Layout Versus Schmatic).
I can create a Spice netlist from the IC Layout (even from the digital part).
The usual way is to compare this with a netlist, created from the schmatic
editor.
I know, this sounds very complicated when you know the CAD flow for PCB
design. I personaly moved one year ago from PCB to ASIC design and was
shocked about this uncomfortable methode.
Never the less, if we find a solution to this problem with the device
property, I can use gschem for my development.
Gruesse in die neue Welt
Peter
Hi, Kaiser.
I am also trying to use gschem for a chip design. However, I'm doing a
structured-ASIC base, rather than a mixed signal ASIC.
I think I see why you need both the Verilog and SPICE netlisters to
work... Your analog stuff is all done in schematics, but for LVS, your
back-end guys want a Verilog netlist. Is that right?
I don't see why this can't be made to work.
I'll go ahead and guarentee that a back-end netlister will be available
that does what you need for both SPICE and Verilog. Feel free to start
your work in gschem, and if you run into trouble with gnetlist, I'll
enhance gdatabase to do what's needed.
I originally had some trouble with hierarchy in gnetlist, and I was
looking for a good reason to build an open-source EDA database for gEDA.
I went ahead and wrote a new EDA database, and a new SPICE netlister on
top of it. It currently only writes out SPICE netlists, but I can add
Verilog. It doesn't currently flatten the netlist, so the output is
hierarchical. The gdatabase SPICE netlister does not use the DEVICE
attribute at all, so you're free to use it for the Verilog netlister.
I've always wanted to write a simple LVS tool. I know you wont want to
use it on your design, but I've been looking for simple things I can do
with the new database code. I've never understood why LVS takes so
long. Is there any chance I could test out some new LVS code on your
design? You could run it for me if you aren't able to give out the
netlists.
Bill