Re: gEDA-user: one schmatic ==> two netlist

[Die.Kaisers@t-online.de (Familie Kaiser)]

Hi Cox,


> Hi, Kaiser.
>
> I am also trying to use gschem for a chip design.  However, I'm doing a
> structured-ASIC base, rather than a mixed signal ASIC.

It is always nice to find new friends.

> I think I see why you need both the Verilog and SPICE netlisters to
> work...  Your analog stuff is all done in schematics, but for LVS, your
> back-end guys want a Verilog netlist.  Is that right?

I need the verilog for digital simulation. For LVS I need a spice netlist.

> I don't see why this can't be made to work.

Me too. I just try to figure out the best and easiest way to do this.

> I'll go ahead and guarentee that a back-end netlister will be available
> that does what you need for both SPICE and Verilog.  Feel free to start
> your work in gschem, and if you run into trouble with gnetlist, I'll
> enhance gdatabase to do what's needed.

Thank you. What do you meen with "enhance gdatabase"? Is it changing the 
netlister or doing something in the database.


> I originally had some trouble with hierarchy in gnetlist, and I was
> looking for a good reason to build an open-source EDA database for gEDA.
>  I went ahead and wrote a new EDA database, and a new SPICE netlister on
> top of it.  It currently only writes out SPICE netlists, but I can add
> Verilog.  It doesn't currently flatten the netlist, so the output is
> hierarchical.  The gdatabase SPICE netlister does not use the DEVICE
> attribute at all, so you're free to use it for the Verilog netlister.

I will do some further testing with the properties.

> I've always wanted to write a simple LVS tool.  I know you wont want to
> use it on your design, but I've been looking for simple things I can do
> with the new database code.  I've never understood why LVS takes so
> long.  Is there any chance I could test out some new LVS code on your
> design?  You could run it for me if you aren't able to give out the
> netlists.

Sure. I will prepare something for you.

Peter