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Re: Vendor FPGA tools (was Re: gEDA-user: Re: Pointer to 3d CAD?)
Dave -
On Wed, Nov 08, 2006 at 08:40:26AM -0500, Dave McGuire wrote:
> On Oct 31, 2006, at 1:40 AM, ldoolitt@xxxxxxxxxxxxxxx wrote:
> >After [Xilinx XST is] installed, I too use the command-line-only
> >programs. With some scripting, they embed nicely in my Makefiles.
>
> I've about had it with the Xilinx GUI. Would you be willing to
> share your Makefiles?
Here's a Makefile snippet:
SYNTH = inch.v ad95xx_driver.v source.v freq_count.v trace.v rx_buffer.v generic_fifo_dc_gray.v generic_dpram.v dds.v cordic.v
# test build, mostly a syntax check
inch: ${SYNTH} BUFG.v
iverilog -DTARGET_s3 -Wall $^ -o $@
# synthesize a bitfile
_xilinx/inch_s3.bit: ${SYNTH}
arch=s3 sh runme inch_s3 $^
where the real work happens in runme, which I will both attach
and post to http://recycle.lbl.gov/~ldoolitt/xilinx/runme
That script is somewhat organic, I have added some odd features
over the past couple of years. Like the ability to automatically
create a .ucf file with timing goals in it based on the comments
in the top level Verilog module:
module stacker(
input clk, // timespec 6.5 ns
input gate,
...
which is useful for keeping track of timing and cell usage for
each of the components of a design.
The other major features of the script are:
- immediate exit with failure if $XILINX is not set
- target chip determined by $arch input
- all 22 scratch and log files pushed into _xilinx directory
- exits with failure if timing constraints not met
One defect in the script is that it doesn't split the synthesis
and P&R steps, so changing the ucf file requires resynthesis.
I find most of the time is spent in the P&R, so my motivation
to split them is small.
I hope this helps. If more than two of us start using a script
like this, I'll post a web page to keep track of ideas and
script variants.
- Larry
# This script places all scratch files, and the resulting .bit file,
# in the _xilinx directory. Tested with XST 7.1i.
# Default architecture is s3
if [ -z "$arch" ]; then arch=s3; fi
if [ "$XILINX" = "" ]; then
echo "set up for Xilinx first" >&2
exit 1
fi
set -e
mkdir -p _xilinx
cd _xilinx
# DESIGN=stacker
DESIGN=$1
shift
PART_s3=xc3s1000-ft256-4
CLOCK_PIN=P125
#PART_s3=xc3s400-ft256-4
#CLOCK_PIN=T9
eval PART=\$PART_$arch
cat <<EOT >$DESIGN.xst
set -tmpdir .
run
-ifn $DESIGN.prj
-ifmt Verilog
-ofn $DESIGN
-ofmt NGC
-p $PART
-top $DESIGN
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator _
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-vlgincdir
-fsm_extract YES -fsm_encoding Auto
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-mux_extract YES
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-resource_sharing YES
-iobuf YES
-max_fanout 100
-bufg 4
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-slice_packing YES
-iob auto
-slice_utilization_ratio_maxmargin 5
EOT
BOMB=""
toplevel=$1
echo "\`define TARGET_$arch 1" >$DESIGN.prj
for s; do
test -r ../$s || BOMB="$BOMB $s"
echo "\`include \"../$s\""
done >>$DESIGN.prj
# sed -e 's/^/\`include "..\//' -e 's/$/"/' ../$DESIGN.set
echo "\`include \"$XILINX/verilog/src/iSE/unisim_comp.v\"" >>$DESIGN.prj
# If the ${DESIGN}.ucf file doesn't exist, create one based on
# comments in the top level Verilog.
ucf=../${DESIGN}.ucf
if [ ! -r $ucf ]; then
ucf=${DESIGN}.ucf
perl -ne 'if (/(\w+),\s+\/\/ timespec\s+(.+)/) {print "NET \"$1\" LOC=\"'${CLOCK_PIN}'\";\nNET \"$1\" TNM_NET = \"CLK_1\";\nTIMESPEC \"TS_CLK_1\" = PERIOD \"CLK_1\" $2 HIGH 50%;\n"}' ../$toplevel >$ucf
fi
test -r $ucf || BOMB="$BOMB $ucf"
if [ -n "$BOMB" ]; then
echo "missing files:$BOMB" >&2
exit 1
fi
# exit
# demote USB_IFCLK error to a WARNING
export XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING=1
xst -ifn $DESIGN.xst -ofn $DESIGN.syr
ngdbuild -dd . -uc $ucf -p $PART $DESIGN.ngc $DESIGN.ngd
# was "-cm area"
map -p $PART -timing -cm speed -ol high -pr b -k 4 -c 100 -tx off -o ${DESIGN}_map.ncd $DESIGN.ngd $DESIGN.pcf
par -w -ol high -t 1 ${DESIGN}_map.ncd $DESIGN.ncd $DESIGN.pcf
# optional (timing report)
trce -e 3 -l 3 $DESIGN.ncd -o $DESIGN.twr $DESIGN.pcf
if grep "All constraints were met\." $DESIGN.par &&
grep "All signals are completely routed\." $DESIGN.par; then
echo "PAR success confirmed for $DESIGN"
else
echo "PAR apparently failed for $DESIGN"
exit 1
fi
bitgen -w -g StartUpClk:JtagClk $DESIGN.ncd
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