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Re: gEDA-user: connecting symbols that look nothing like their footprint
On 11/17/06, Meador, Ryan D <rmeador@xxxxxxx> wrote:
This issue has also come up with parts that have
many ground connections, such as the ADXL321 accelerometer; it would be
logical for the symbol to have 1 ground pin connected to many physical pins,
but until I ran up against this problem with the FET, I just lived with
making the symbol look like the package.
Note: I understand how I can have a
symbol such as an op-amp which hides the power and ground pins; I just don't
know how to connect a single symbol pin to multiple physical pins. I thought
about using the net attribute, but then I think all instances of my symbol
would end up connected together?
When you are troubleshooting your circuit it is useful to know where
all the physical
pins are connected. If you start eliminating pins from your schematic symbols
you will lose that information. You will not known whether a pin was
Vdd, GND, Vss.
It gets worse for components that operate with multiple isolated grounds (like
isolation amplifiers and isolated DC-DC converters).
Avoid using symbols that hide the power and grounds. You may want to run
a dual-supply amplifier off a single power supply which means connecting Vee to
GND. You may want to connect two isolated DC-DC converters together to get a
positive and negative output which means connecting the output return of one
converter to the output of the other converter. If the nets are embedded you
will not be able to do this.
You can make a symbol with just power and ground connections. If
multiple symbols
have the same refdes they will be treated as a single part.
I have included a short schematic (below) that shows how I like to do power
and connections.
(* jcl *)
--
http://www.luciani.org
------- cut here --------
v 20050313 1
C 54400 66800 1 0 0 EMBEDDEDcapacitor.sym
[
P 54600 67300 54600 67100 1 0 0
{
T 54650 67500 5 8 0 1 0 0 1
pinnumber=1
T 54650 67500 5 8 0 0 0 0 1
pinseq=1
}
P 54600 66800 54600 67000 1 0 0
{
T 54650 66900 5 8 0 1 0 0 1
pinnumber=2
T 54650 66900 5 8 0 0 0 0 1
pinseq=2
}
L 54800 67100 54400 67100 3 0 0 0 -1 -1
L 54800 67000 54400 67000 3 0 0 0 -1 -1
T 55000 67200 5 10 0 0 0 0 1
device=CAPACITOR
T 54400 66800 8 10 0 1 0 0 1
pins=2
T 54400 66800 8 10 0 1 0 0 1
class=DISCRETE
]
{
T 54700 67200 5 10 1 1 0 0 1
refdes=C?
T 54700 66900 5 10 1 1 0 2 1
value=?
}
C 66800 65400 1 0 0 EMBEDDEDcapacitor.sym
[
P 67000 65900 67000 65700 1 0 0
{
T 67050 66100 5 8 0 1 0 0 1
pinnumber=1
T 67050 66100 5 8 0 0 0 0 1
pinseq=1
}
P 67000 65400 67000 65600 1 0 0
{
T 67050 65500 5 8 0 1 0 0 1
pinnumber=2
T 67050 65500 5 8 0 0 0 0 1
pinseq=2
}
L 67200 65700 66800 65700 3 0 0 0 -1 -1
L 67200 65600 66800 65600 3 0 0 0 -1 -1
T 67400 65800 5 10 0 0 0 0 1
device=CAPACITOR
T 66800 65400 8 10 0 1 0 0 1
pins=2
T 66800 65400 8 10 0 1 0 0 1
class=DISCRETE
]
{
T 67100 65800 5 10 1 1 0 0 1
refdes=C1
T 67100 65500 5 10 1 1 0 2 1
value=0.1uF
}
C 68000 65500 1 0 0 EMBEDDED74x1G14.sym
[
L 68300 65700 68300 66300 3 0 0 0 -1 -1
L 68300 66300 68800 66000 3 0 0 0 -1 -1
L 68800 66000 68300 65700 3 0 0 0 -1 -1
V 68850 66000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 68000 66000 68300 66000 1 0 0
{
T 68200 66050 5 8 1 1 0 6 1
pinnumber=2
T 68200 65950 5 8 0 1 0 8 1
pinseq=1
T 68350 66000 9 8 0 1 0 0 1
pinlabel=A
T 68350 66000 5 8 0 1 0 2 1
pintype=in
}
P 69200 66000 68900 66000 1 0 0
{
T 69000 66050 5 8 1 1 0 0 1
pinnumber=4
T 69000 65950 5 8 0 1 0 2 1
pinseq=2
T 68750 66000 9 8 0 1 0 6 1
pinlabel=Y
T 68750 66000 5 8 0 1 0 8 1
pintype=out
}
T 68300 66900 5 10 0 0 0 0 1
slot=1
T 68300 66700 5 10 0 0 0 0 1
numslots=1
T 68300 66500 5 10 0 0 0 0 1
device=74x1G14
L 68390 66060 68390 65860 3 0 0 0 -1 -1
L 68390 65860 68450 65900 3 0 0 0 -1 -1
L 68390 66060 68450 66100 3 0 0 0 -1 -1
L 68390 65860 68330 65820 3 0 0 0 -1 -1
L 68450 65900 68450 66100 3 0 0 0 -1 -1
L 68450 66100 68520 66140 3 0 0 0 -1 -1
T 68300 68700 5 10 0 0 0 0 1
pins=5
T 68300 69100 5 10 0 0 0 0 1
description=single inverting Schmitt-trigger
T 68300 69500 5 10 0 0 0 0 1
footprint=SC70-65P-210L1-5N__LTC_SC6-Package
]
{
T 68600 66200 5 10 1 1 0 0 1
refdes=U1
}
C 66500 65300 1 0 0 EMBEDDED74x1G14_pwr.sym
[
P 66600 65900 66600 65800 5 0 0
{
T 66600 65775 5 6 1 1 0 5 1
pinlabel=Vcc
T 66625 65825 5 6 1 1 0 0 1
pinnumber=5
}
P 66600 65400 66600 65500 5 0 0
{
T 66600 65525 5 6 1 1 0 3 1
pinlabel=GND
T 66625 65475 5 6 1 1 0 2 1
pinnumber=3
}
]
{
T 66575 65825 5 6 1 1 0 6 1
refdes=U1
}
N 68000 66000 67900 66000 4
N 67900 66000 67900 65900 4
C 66800 66100 1 0 0 EMBEDDED+5V.sym
[
P 67000 66100 67000 66150 1 0 0
{
T 67050 66150 5 6 0 1 0 0 1
pinnumber=1
T 67050 66150 5 6 0 0 0 0 1
pinseq=1
}
V 67000 66200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 67000 66275 9 8 1 0 0 3 1
+5V
T 67100 66100 8 8 0 0 0 0 1
net=+5V:1
]
C 66900 65000 1 0 0 EMBEDDEDgnd.sym
[
P 67000 65150 67000 65200 1 0 1
{
T 67058 65161 5 4 0 1 0 0 1
pinnumber=1
T 67058 65161 5 4 0 0 0 0 1
pinseq=1
}
L 66900 65150 67100 65150 3 0 0 0 -1 -1
L 66900 65150 67000 65050 3 0 0 0 -1 -1
L 67000 65050 67100 65150 3 0 0 0 -1 -1
T 67200 65050 8 10 0 0 0 0 1
net=GND:1
]
C 67800 65700 1 0 0 EMBEDDEDgnd.sym
[
P 67900 65850 67900 65900 1 0 1
{
T 67958 65861 5 4 0 1 0 0 1
pinnumber=1
T 67958 65861 5 4 0 0 0 0 1
pinseq=1
}
L 67800 65850 68000 65850 3 0 0 0 -1 -1
L 67800 65850 67900 65750 3 0 0 0 -1 -1
L 67900 65750 68000 65850 3 0 0 0 -1 -1
T 68100 65750 8 10 0 0 0 0 1
net=GND:1
]
N 67000 65400 67000 65200 4
N 66600 65400 66600 65300 4
N 66600 65300 67000 65300 4
N 66600 65900 66600 66000 4
N 66600 66000 67000 66000 4
N 67000 66100 67000 65900 4
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