Re: gEDA-user: PCB 20070912 surprising silk behavior

[Ben Jackson <ben@xxxxxxx>]

On Mon, Nov 26, 2007 at 06:37:27PM -0800, Dave N6NZ wrote:
> 
> My board has solid polygons going out to the edge on the back side.

That's generally a bad idea because it will cause the edge of the board
to be "hot" if you touch it right.  I have a protoboard (not designed
by me!) that has that bug and I caused it to short out many times before
I realized what was happening.

Also, many fabs are not going to allow you to have any copper features
that close to the edge.

> 2) The lines were drawn with "clearpoly", clearing the edges of my 
> polygons. I had "new lines clear polygons" turned on.

That makes it seem very unlikely to me that your lines are really on a
"back silk" layer.

> 2) I can't imagine why a line drawn on the silk layer should clear a 
> solder-side polygon.

IIRC, I posted a month ago about my discovery that lines don't even
clear polygons on silk layers.  I don't know why that exception is
even there, but again it makes me think you did not draw on a silk
layer.

You should check the gerber output very carefully.

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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