Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

[Andy Peters <devel@xxxxxxxxx>]

On Nov 28, 2007, at 1:49 PM, Ben Jackson wrote:

> On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller  
> wrote:
>>
>> We've discovered that the clock generators in the Xilinx FPGA part  
>> are
>> lousy for generating video clocks.
>
> DCMs have lousy jitter, yes.

Indeed. The Spartan 3E claims +/- 100 ps jitter on the DCM's CLK0 (in- 
phase) output and +/- 150 ps on the CLK90, CLK180 and CLK270 (phase- 
shifted) outputs. The clock-doubler outputs claim +/- 1% of the clock- 
in period + 150 ps jitter.  When doing integer division, the CLKDV  
outputs claim +/- 150 ps jitter. When doing non-integral division, the  
CLKDV output claims +/- 1% of the clock-in period + 200 ps jitter.  
Then when one reads the footnotes, one learns that these numbers are  
in addition to any input clock jitter.

-a


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