Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

[Ben Jackson <ben@xxxxxxx>]

On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote:
> 
> We've discovered that the clock generators in the Xilinx FPGA part are
> lousy for generating video clocks.

DCMs have lousy jitter, yes.  Altera parts have real PLLs, though.

> which causes artifacts on DVI monitors at resolutions as low as
> 1280x1024 when the cable gets beyond a certain length.  (I don't
> recall all the details.)

That's kind of surprising, because the DVI spec has a bitrate 10x the
fundamental clock, so both the transmitter and receiver generally have
to have PLLs.

> So the best solution we can come up with is to put on some external
> clock generators.

Cypress makes a bunch, and some inexpensive devboards called "candy
boards", eg peppermint.

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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