Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

Timothy -

On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote:
> We've discovered that the clock generators in the Xilinx FPGA part are
> lousy for generating video clocks.

Welcome to the club.

> So the best solution we can come up with is to put on some external
> clock generators.  One for each video head.  Problems:  (1) more time
> to mod the design, (2) up to $15 each for the generators, (3) we have
> no idea what generators to use, how good they are, how to wire them.
> 
> Does anyone know anything about these?  Do you have experience with
> specific high-frequency clock generators and know how they perform and
> what kind of jitter they produce?

I live and breathe high-frequency clock jitter.  A good clock
subsystem has less than 1 ps rms clock jitter, at least in a
limited band (e.g., 20 Hz to 20 MHz).  Bad layout can screw up
a design even if you use good parts.

I have had positive experience with parts from ICS and AD.
My experience is not specific to video.

> Unfortunately, it could take quite a long time for us to find
> suppliers of clock generators, get samples, wire them up and test
> them, etc., so we just need find out if someone out there already has
> the right answer or knows where to look for it.

You haven't mumbled enough about the specific needs for me to help
much yet.  Frequency range, degree of programmability, signal levels,
etc.  Do you need a PLL, or is a programmable divider chain enough?
An AD9512 is a nice part, and "only" US$20 each, with several
programmable outputs.

   - Larry


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