Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

Ben -

On Wed, Nov 28, 2007 at 12:49:50PM -0800, Ben Jackson wrote:
> On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote:
> > 
> > We've discovered that the clock generators in the Xilinx FPGA part are
> > lousy for generating video clocks.
> 
> DCMs have lousy jitter, yes.  Altera parts have real PLLs, though.

Even if the FPGA chip were perfect, there are so many digital signals
flying around the package that ground bounce alone will kill any semblance
of low jitter performance.

This may be too fine a point for video work.  My work involves SDR-like
projects where the requirements on the order of 1ps rms.

> > which causes artifacts on DVI monitors at resolutions as low as
> > 1280x1024 when the cable gets beyond a certain length.  (I don't
> > recall all the details.)
> 
> That's kind of surprising, because the DVI spec has a bitrate 10x the
> fundamental clock, so both the transmitter and receiver generally have
> to have PLLs.

Just the receiver, right?  And that cable length comment makes me
suspicious something more subtle is going on.

   - Larry


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