Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

[Ben Jackson <ben@xxxxxxx>]

On Wed, Nov 28, 2007 at 01:02:00PM -0800, Larry Doolittle wrote:
> > 
> > DCMs have lousy jitter, yes.  Altera parts have real PLLs, though.
> 
> Even if the FPGA chip were perfect, there are so many digital signals
> flying around the package that ground bounce alone will kill any semblance
> of low jitter performance.

The Altera PLLs have dedicated supply (and output) pins and are located
in the corners of the chip.  The Xilinx DCMs are on the 2.5V VCCAUX rail
shared with other things.  I suppose it's worth seeing if the original
board would perform better with a cleaner VCCAUX, but the nature of a
DCM is inherently jittery.

> This may be too fine a point for video work.  My work involves SDR-like
> projects where the requirements on the order of 1ps rms.

At work I'm on a project that is generating high bandwidth signals up
to 1G and our LOs are custom PLL modules (small boards with can lids)
from Mini Circuits.  Sounds like overkill for DVI, though.

> > That's kind of surprising, because the DVI spec has a bitrate 10x the
> > fundamental clock, so both the transmitter and receiver generally have
> > to have PLLs.
> 
> Just the receiver, right?  And that cable length comment makes me
> suspicious something more subtle is going on.

I've looked at receivers more closely than transmitters, but I assume
that the input to the transmitter is the fundamental clock plus the
wide (32?  36?) bit RGB+control plane.  The serial output has the
10x bitrate, so it must make it internally.  One from Conexant I just
googled shows a PLL in the block diagram.

My point being that the transmitter chip should be fine as long as
the jitter does not impact setup-and-hold times at the input and the
PLL rides over it.  Is there an external loop filter to play with?

Ohh it just occured to me that perhaps the problem is that the 10x clock
is made from the PLL but the CLK signal on the DVI is the original clock,
not a divide-by-10 of the PLL.  In that case maybe there are transmitters
where this is different?

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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