gEDA-user: PCB Copy / Panellizing

[Tony Radice <tradice1@xxxxxxxxxxx>]

Gentlemen - 
    First - Ineiev and Peter - Thank you for the replies. This was
indeed a combination of my errors - 

a) I pulled the latest cvs per DJ's instructions and re-compiled. Not
only did the fills come out properly, but the software behaves MUCH
faster!  My complements on the two fixes.

b) You are both correct on the grouping - I normally add an "Outline"
layer as the top most on the layers, I failed to do this on the D-Sheet
template, resulting in an incorrect layer configuration when I pasted
from a board file that DOES have the correct layer stack.

Now - perhaps two questions for other poor schlubs like me who have to
be hit over the head with a baseball bat to get a point through our
thick skulls: 

1) What does "can you check the current GIT head" mean? How does one do
that? 

2) Is there a written procedure on how the development team would like
potential bugs submitted and checked?  If so, where? I would rather not
submit 1 M files for review (Yes, Peter!! ;-)) - and (although I WILL do
this next time) perhaps a checklist of "Is this the latest release" - do
this first - may be helpful? 

Thank you again for your advice and help!!

Tony Radice

P.S. Who CARES how "panellizing" is spelled - do we graded on spelling
here? WE all know what we are speaking about - don't we??  ... on second
thought.. ;-)



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