Re: gEDA-user: How to deal with single/dual parts?

[John Doty <jpd@xxxxxxxxx>]

On Nov 18, 2009, at 11:54 AM, Bill Gatliff wrote:

> Stephan Boettcher wrote:
>> I'd not call that abuse.  The current sloting mechanism allows to  
>> change
>> pin numpers on a drawn component to switch to a different instance  
>> of the
>> component inside the same package.
>>
>> We also call for changing pin numbers when we replace one package  
>> type
>> with another.  What is so bad proposing to generalize the existing
>> mechanism to cover both cases cleanly, instead of implementing  
>> another
>> mechanisem that does almost the same?
>>
>
> Not sure if this question is related, but...
>
> Why not change the workflow so that during schematic capture, there  
> are
> no pin numbers anywhere?

Let's not say "change the workflow". There are many workflows. Pin  
numbers and packages are already irrelevant to some.

>   "Pins" on symbols get assigned a physical pin
> number during some some later step, at the same time that  
> footprints are
> selected.

Have a tool that translates schematics without pin numbers to  
schematics with them.

>   And then a backwards data flow brings the pin assignments
> back to gschem for display?

Well, I wouldn't want to have a backwards data flow that mucks with  
my source schematics. But having the tool output .sch format means  
you can print the version with pin numbers for documentation. I  
wouldn't edit such schematics. But you could if that's what you want.

>   Of course, I really have little idea of the
> implications of what I'm saying...  :)
>
> It has never made sense to me to do pin assignments during schematic
> capture.

Yes.

>   At that point, all I'm interested in is the signal flow
> through the symbols--- the pin assignments aren't a necessity until
> layout, and are subject to change during layout in ways that don't
> really affect the schematic.

You can't select an opamp without knowing its requirements, and it's  
hard to know those without the schematic.

>   I don't really care that I chose a chip
> with four NAND gates rather than four single-chip ones, the logical
> signal flow is the same in both cases.  But that change often requires
> that I physically change from one symbol to another in gschem, even  
> when
> the visual representations are identical.
>
> Of course, you have to deal with making sure that the four-gate  
> chip has
> a decoupling capacitor vs. four caps for the four-chip solution, and a
> convenient way to note that is on some power-related pages attached to
> your schematic diagram.

A specialized tool to autogenerate such pages would be useful, too.  
But such functionality does not belong in gschem itself.

>   But I find that almost everyone puts those on
> their own pages, so that they don't "pollute" the rest of their
> schematic.  That suggests to me that other people view schematic
> diagrams as logical entities too, at least except for those
> power-related pages.
>
> Because of what I view the schematic capture process as being, stuff
> like slotting and footprint= don't really fit in with my mental  
> model of
> what schematic symbols are.  As I see it, those concepts exist only
> because we're trying trying to force part of the layout process  
> upstream
> into schematic capture.

Yes!

>   I don't know how to fix the problem, but I
> think that's what it is.
>
> Obviously, you can't eliminate pin numbers altogether in a schematic
> diagram.  How would I know where to put my oscilloscope probe?  :)   
> But
> a schematic diagram that features pin numbers is a subtly different
> document from one that doesn't--- it contains "markup" recording
> decisions made during layout.

You want to "print out" flat "documentation" schematics with pin  
numbers, part values, etc. But you should be able to leave these out  
of the abstract "source" schematics you capture, put them in at a  
later stage.

>
> Just my $0.02.
>
>
> b.g.
>
> -- 
> Bill Gatliff
> bgat@xxxxxxxxxxxxxxx
>
>
>
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John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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