Re: gEDA-user: How to deal with single/dual parts?

[John Doty <jpd@xxxxxxxxx>]

On Nov 18, 2009, at 1:23 PM, Peter Clifton wrote:

> On Wed, 2009-11-18 at 10:56 -0700, John Doty wrote:
>> On Nov 18, 2009, at 9:11 AM, Peter Clifton wrote:
>
>> So I think what you're saying is that you like the idea of a tool
>> that converts (hierarchical .sch)->(flat .sch).
>
> That can't work if there isn't some extra information input somewhere.

You can *flatten* without extra info. You can't go all the way to a  
concrete implementation without extra info.

> On the one hand you're saying that the hierarchical schematic contains
> an abstract logical circuit diagram, on the other - that the
> implementation will violate that hierarchy by sharing - say, an ADC  
> with
> multiple channels.

The tool that implements the sharing could be separate from the tool  
that does the flattening. That is desirable, as the input schematics  
may or may not be flat to begin with. Orthogonal design.

>
> Simply flattening the logical hierarchy doesn't tell you how it was
> implemented in terms of slots / chips used.

True, but irrelevant. Flattening is a logically independent function.

>
>
> In the designs I've done with hierarchy, I kept the hierarchy matching
> the physical implementation. That means dropping a level of sub- 
> circuit
> when you get to things like multi-channel ADCs, or op-amps with slots
> shared between two logical channels.

Me, too. It gets messy, though, when dealing with chips that have  
lots of channels, chips that have incommensurate slot counts, or  
cases where you don't use all of the channels in each block.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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