Re: gEDA-user: How to deal with single/dual parts?

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Wed, 2009-11-18 at 10:56 -0700, John Doty wrote:
> On Nov 18, 2009, at 9:11 AM, Peter Clifton wrote:

> So I think what you're saying is that you like the idea of a tool  
> that converts (hierarchical .sch)->(flat .sch).

That can't work if there isn't some extra information input somewhere.
On the one hand you're saying that the hierarchical schematic contains
an abstract logical circuit diagram, on the other - that the
implementation will violate that hierarchy by sharing - say, an ADC with
multiple channels.

Simply flattening the logical hierarchy doesn't tell you how it was
implemented in terms of slots / chips used.


In the designs I've done with hierarchy, I kept the hierarchy matching
the physical implementation. That means dropping a level of sub-circuit
when you get to things like multi-channel ADCs, or op-amps with slots
shared between two logical channels.





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