Re: gEDA-user: PCB+GL Testers (please test)

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Wed, 2010-11-03 at 21:54 +0100, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
> 
> > If VBO rendering slows you down,
> 
> Ehm, how would I know, that this is the the actual bottle neck?
> (What is VBO, anyway?)

Vertex buffer object:

http://en.wikipedia.org/wiki/Vertex_Buffer_Object

> 
> 
> > Throw your "usual" complexity of board at it.
> 
> Tried it at work. This is a 3.5 years old, moderate hardware. AMD single
> processor, 4400 BogoMIPS. Graphics card is nvidia  NV37GL Quadro PCI-E Series. 
> Graphics driver is the closed source "nvidia, 173xx legacy version". Pcb was 
> run in a maximized window on my left 1280x1024  monitor.
> 
> pd-ac:
> (a small board)
> http://bibo.iqo.uni-hannover.de/dokuwiki/doku.php?id=eigenbau:photodiodenverstaerker_20_mhz
> pcb-head (compiled in August 2010: 35 FPS (thin_draw_poly:44 FPS)
> pcb-GL_before_pours: 20 FPS
> pcb_local_customisation_no_pours: 20 FPS
> 
> pidpeltier:
> (a more koomplex board)
> http://bibo.iqo.uni-hannover.de/dokuwiki/doku.php?id=eigenbau:temperaturregler_diodenlaser
> current debian/squeeze pcb-gtk, version 20091103: 25 FPS
> pcb-head: 12.5 FPS
> pcb-GL_before_pours: 16.5 FPS
> pcb_local_customisation_no_pours: 12 FPS
>  
> lasertreiber:
> (My most complex real world board. I usually switch off polygon planes)
> http://bibo.iqo.uni-hannover.de/dokuwiki/doku.php?id=eigenbau:lasertreiber
> current debian/squeeze, version 20091103: 17 FPS (thin draw poly 25: FPS)
> pcb-head: 11 FPS (thin_draw_poly:18 FPS)
> pcb-GL_before_pours: 9 FPS
> pcb_local_customisation_no_pours: 10 FPS
> 
> Looks like v20091103 is consistently the fastest binary on this particular 
> set-up. Any idea, why this is so?

Hmm, that is interesting. Just note that the stock PCB's thindraw poly
is faster, but the PCB+GL one will actually increase the workload due to
the fancy translucency it does in that mode.

It is interesting to note that git HEAD PCB is slower than 20091103. I
wonder what I broke ;) (There might be some performance trade-offs which
have been made to improve other activities).

I might have to dig into that, as it is quite a worrying regression on
some of the boards.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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