gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?

[Chris <i_chris_pa@xxxxxxxxx>]

    Hello mailing list,
    I need some help here. I want to use gschem to create a hierarchical
    design and simulate that using icarus verilog. "gnetlist -g verilog"
    works fine, but I have some trouble figuring out how to create a
    matching symbol for the schematic and using gnetlist to assign module
    parameters in a certain order.
    In particular, I can't figure out how to enforce the module parameter
    order in the verilog file by assigning attributes to my schematic and
    symbols. I suspect that the pinnumber of the symbol are somehow matched
    to the INPUT# values of the schematics pads, but I can't find any
    documentation how that is done (and reading the
    /usr/share/gEDA/scheme/gnet-verilog.scm was also not all too helpfull).
    Starting of with the basics, I built a rs-flipfop schematic with the
    inputs A,B,CLK,Q and nQ. I want the module created with "gnetlist -g
    verilog" to create the module with that exact parameter order, that is
    it should produce a header looking like "module rs_ff ( S, R, CLK, Q,
    nQ);". Instead when I convert the schematic, I end up with a "module
    rs_ff (R,CLK,S,nQ,Q)". Pinnumber, Pinsequence and Pintypes ("INPUT0",
    "OUTPUT0"...) are set on the ipads and opads but obviously get ignored.
    I then created a symbol for the rs-flipflop (pinnumbers, pinsequence
    and pintypes of the same value as those of the pads in the schematic)
    and placed it into a schematic file forming a d-flipflop. The input
    nets and output net are correctly translated to the module parameter
    order, but I am not sure if this is just luck or not.
           RS_FF.sym                Verliog assignment
           ________
         0|       |3                rs_ff rs_ff0 (nD,CLK,D,nQ,Q);
    --D--=|S     Q|=---Q----
         1|       |
    -CLK-=|CLK    |
         2|       |4
    --nD-=|R    nQ|=---nQ---
          |_______|
          RS_FF.schm                Verilog Assignement
     __
    |S \_netname=S__ ...
    |__/                 __
        ..._netname=Q___/ Q|        module (R,CLK,S,Q,nQ);
                        \__|
     __
    |C \_netname=CLK_ ...
    |__/                 __
        ..._netname=nQ__/nQ|
                        \__|
     __
    |R \_netname=R__ ...
    |__/
    I can't really get a grip on which pin of the symbol get's assigned to
    which pin of the hierarchically underlying schematic when a schematic
    containing the symbol get's converted to verilog. Equally, when running
    the symbol's schematic through gnetlist I can't control in what order
    the Inputs and Outputs get listed as module Parameters.
    How can I enforce a certain parameter order in verilog modules when
    using ipads and opads in a schematic or pins in a symbol?
    Thanks for you help and time,
    Cheers,
    Chris


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