Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?

[Paul Tan <pt75234@xxxxxxx>]

Hi Chris,

Last time I checked, when netlisting a schematic, the
gEDA Verilog netlister does not order the top MODULE portnames
by user specified sequence order(such as using the refdes
attribute's numeric suffix value of I/O PADS to order the
portnames).

Since most Verilog simulators (including Icarus Verilog)
support "EXPLICIT connection" method for the lower level
Module Instanciations, so it is not absolutely necessary
(although desirable) to match the Module portname order
with the Module instantiation portname order.

The following hierarchical netlist format is legal in Verilog.
//====================================
module DFF ( R, D, C, ... );
wire R;
...
end module;
//--------------------
module REGX32 (DBUS, CLK, RD, WR, RST, ...);
wire [31:0] DBUS;
wire CLK;
....
// Modules instantiations
DFF U1 (
  // portname   connected-signal-netname
     .D           ( DBUS[0] ),
     .C           ( CLK ),
     .R           ( RST ),
  ...
);
...
end module;
//====================================

However, last time I checked, Icarus Verilog does not
support EXPLICIT connection method when wire connects
to Verilog Primitives, such as pmos, nand, xor, etc.
So your Primitive Instantiation section of your netlist
should look like the following "IMPLICIT" connection:

nand U5 (
   // portname(commented out)  connected netname
   /* OUT */                   net1,
   /* IN0 */                   net2,
   /* IN1 */                   net3
);

gEDA Verilog netlister handles this situation correctly
if you add to all the primitive symbols (nand, etc) the
attribute "VERILOG_PORTS=POSITIONAL", and if you make
sure your symbol file, e.g.,and8-1.sym (open in text editor) list
the "pinnumber=???" in top to bottom order. Refer to the stocked
Verilog symbol file and8-1.sym file as an example:
    pinnumber=OUT
    pinnumber=IN0
    .....
    pinnumber=IN7

(please refer to the gEDA document "README.verilog" file or
the gEDA wiki).

Best Regards,
Paul Tan


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