Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?

[Paul Tan <pt75234@xxxxxxx>]

Hi Chris,

On Sunday 21 November 2010, Chris wrote:
> Btw: The bufif1 symbol from the verilog library get's compiled with
> it's inputs in the wrong order. That is the gnetlist -g verilog
> produced bufif1(IN,OUT,CNTRL) instead of bufif1(OUT,IN,CNTRL). How can
> I change that? I changed the INPUT0 and INPUT1 statements in the
> attributes of the pins, but that didn't change anything.

There is a problem with the stocked bufif1-1.sym file. (may be others 
too).
The Verilog standard requires the primitive bufif1 to
use the port order:
  bufif1(output, input, control).

Changing the order require cut/paste the entire pin definition
section such as:
//==================
P x x x x x x x
{
...
}
//==================

To correct that cut and paste the following (between, but
not including the "//====" lines) and save as your
new bufif1-1.sym file:

//==================================
v 20031231 1
L 300 800 800 500 3 0 0 0 -1 -1
L 800 500 300 200 3 0 0 0 -1 -1
L 300 800 300 500 3 0 0 0 -1 -1
L 300 500 300 200 3 0 0 0 -1 -1
P 1100 500 800 500 1 0 0
{
T 915 550 5 8 0 1 0 0 1
pinnumber=OUTW
T 915 550 5 8 0 0 0 0 1
pinseq=1
}
P 300 500 0 500 1 0 1
{
T 0 550 5 8 0 1 0 0 1
pinnumber=INW
T 0 550 5 8 0 0 0 0 1
pinseq=2
}
P 0 900 550 900 1 0 0
{
T 50 950 5 10 0 1 0 0 1
pinnumber=CONTROLW
T 50 950 5 10 0 0 0 0 1
pinseq=3
}
L 550 900 550 650 3 0 0 0 -1 -1
T 700 750 2 10 0 0 0 0 1
VERILOG_PORTS=POSITIONAL
T 650 250 2 10 0 1 0 0 1
device=bufif1
T 500 300 5 10 1 1 0 2 1
refdes=U?

//==================================

diff the old file with this new one, and see where
the cut/paste occur.


Notes:

1) The above quick fix depends on the SIDE EFFECT of how
the current gEDA core process the symbol file. To really
fix the problem, gnet-verilog.scm needs to be fixed.
For now, it should work.

2) To prevent symbol library problem down the road, try to
follow John Doty advice:
 http://archives.seul.org/geda/user/Nov-2010/msg00425.html

Best Regards,
Paul Tan


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