Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?

[Chris <i_chris_pa@xxxxxxxxx>]

    Hello Al Davis and Paul Tan,
    you solved problem, thank alot. To summarize:
    If I create schematic and assign the attribute 'netname=<name>' to the
    nets coming from our going to the i-/opads and a symbol with the
    attribute 'pinnumber=<name>' at the appropriate pin, they are connected
    explicitly using that name.
    If I want to create a verilog module that accepts parameters in a
    specific order, I have to assign the 'pinnumber=[IN | OUT]<number>' in
    top- to bottom order to the pins of the symbol and the netnames of the
    schematic and include the attribute 'VERILOG_PORTS=POSITIONAL'.
    Cool, thanks :)
    Btw: The bufif1 symbol from the verilog library get's compiled with
    it's inputs in the wrong order. That is the gnetlist -g verilog
    produced bufif1(IN,OUT,CNTRL) instead of bufif1(OUT,IN,CNTRL). How can
    I change that? I changed the INPUT0 and INPUT1 statements in the
    attributes of the pins, but that didn't change anything.
    Cheers,
    Chris
    --- On Sun, 11/21/10, al davis <ad252@xxxxxxxxxxxxxxxx> wrote:

      From: al davis <ad252@xxxxxxxxxxxxxxxx>
      Subject: Re: gEDA-user: control verilog module parameter order when
      converting .sch and .sym with gnetlist?
      To: geda-user@xxxxxxxxxxxxxx
      Date: Sunday, November 21, 2010, 10:07 PM

    On Sunday 21 November 2010, Paul Tan wrote:
    > Since most Verilog simulators (including Icarus Verilog)
    > support "EXPLICIT connection" method for the lower level
    > Module Instanciations, so it is not absolutely necessary
    > (although desirable) to match the Module portname order
    > with the Module instantiation portname order.
    I think it is safe to assume that ALL Verilog simulators support
    the explicit form.  The explicit form is preferred.
    I don't see any practical way that the netlister can reliably
    support connection mapping strictly by order.  It's a real pain
    in Spice.
    If someone is going to improve the Verilog netlister, there are
    other points that really do need to be addressed, such as
    passing parameters and net types other than "wire".  Gnucap
    needs them.
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