Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?

[al davis <ad252@xxxxxxxxxxxxxxxx>]

On Sunday 21 November 2010, Paul Tan wrote:
> Since most Verilog simulators (including Icarus Verilog)
> support "EXPLICIT connection" method for the lower level
> Module Instanciations, so it is not absolutely necessary
> (although desirable) to match the Module portname order
> with the Module instantiation portname order.

I think it is safe to assume that ALL Verilog simulators support 
the explicit form.  The explicit form is preferred.

I don't see any practical way that the netlister can reliably 
support connection mapping strictly by order.  It's a real pain 
in Spice.

If someone is going to improve the Verilog netlister, there are 
other points that really do need to be addressed, such as 
passing parameters and net types other than "wire".  Gnucap 
needs them.


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