Re: gEDA-user: Power nets in hierarchy

[John Griessen <john_g@cibolo.com>]

I too would recommend the option of ports be available, 
by asking for them in a config file, 
for us layout reusing analog oriented types especially... 

By ports, I mean like verilog module ports, where from a net in
one module to a net inside of a module placed in it, the name
of a net can change as it goes through the port.

Example:    What was globally called VSS in a block that is now
merely an instance in another design can connect to one of several
semi-isolated positive voltages in the top level design.


Bill's description of transferring top level power names to a flattened
version of a circuit is just like you do it with verilog design checking.
It's what we need.  We need that along with the options to name nets
and connect power devices to global netnames OR NOT as a particular
designer specifies.   

If we have a module that has a port for power, that port
should override any other specified name if it conflicts.   
For example, if we chose to use global names, and most symbols 
had no power ports -- they were implicit, and one did, and that 
port,  named VSS,  is wired
to a non-global power net called AVSS in the top level, 
I'd like gschem and any DRC run 
to handle it by connecting all the global VSS names to VSS except that one
with its explicit port connection, and generate no error message.

John Griessen

On Wed, 2003-10-22 at 13:55, Carlos Nieves Onega wrote:
> So, I would recommend that there were power ports, and power nets (like
VCC, GND and so on) use those ports to hierarchical connections.

It would make the life simpler and improve the readability of the
designs in a few situations...

Carlos